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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>FMOV (immediate, unpredicated)</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">FMOV (immediate, unpredicated)</h2><p>Move 8-bit floating-point immediate to vector elements (unpredicated)</p>
      <p class="aml">Unconditionally broadcast the floating-point immediate into each element of the destination vector. This instruction is unpredicated.</p>
    <p>
        This is an alias of
        <a href="fdup_z_i.html">FDUP</a>.
        This means:
      </p><ul><li>
          The encodings in this description are named to match the encodings of
          <a href="fdup_z_i.html">FDUP</a>.
        </li><li>The description of <a href="fdup_z_i.html">FDUP</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul>
    <p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td colspan="2" class="lr">size</td><td class="l">1</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td>1</td><td class="r">1</td><td class="lr">0</td><td colspan="8" class="lr">imm8</td><td colspan="5" class="lr">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="FMOV_fdup_z_i_"/><p class="asm-code">FMOV    <a href="#sa_zd" title="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a>.<a href="#sa_t" title="Size specifier (field &quot;size&quot;) [D,H,S]">&lt;T&gt;</a>, #<a href="#sa_const" title="Floating-point immediate value expressable as ±n÷16×2^r (field &quot;imm8&quot;)">&lt;const&gt;</a></p><p class="equivto">
      is equivalent to
    </p>
          <p class="asm-code"><a href="fdup_z_i.html#fdup_z_i_">FDUP</a>    <a href="#sa_zd" title="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a>.<a href="#sa_t" title="Size specifier (field &quot;size&quot;) [D,H,S]">&lt;T&gt;</a>, #<a href="#sa_const" title="Floating-point immediate value expressable as ±n÷16×2^r (field &quot;imm8&quot;)">&lt;const&gt;</a></p>
          <p class="equivto">
          and is always the preferred disassembly.
        </p>
        </div>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zd&gt;</td><td><a id="sa_zd"/>
        
          <p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;T&gt;</td><td><a id="sa_t"/>
        <p>Is the size specifier, 
      encoded in
      <q>size</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">size</th>
                <th class="symbol">&lt;T&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">00</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">01</td>
                <td class="symbol">H</td>
              </tr>
              <tr>
                <td class="bitfield">10</td>
                <td class="symbol">S</td>
              </tr>
              <tr>
                <td class="bitfield">11</td>
                <td class="symbol">D</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;const&gt;</td><td><a id="sa_const"/>
        
          <p class="aml">Is a floating-point immediate value expressable as ±n÷16×2^r, where n and r are integers such that 16 ≤ n ≤ 31 and -3 ≤ r ≤ 4, i.e. a normalized binary floating-point encoding with 1 sign bit, 3-bit exponent, and 4-bit fractional part, encoded in the "imm8" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="fdup_z_i.html">FDUP</a> gives the operational pseudocode for this instruction.</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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